1. Technical Field
The present disclosure relates generally to the forming of interconnect structures in semiconductor devices. In particular, the present disclosure relates to a structure and method of forming an interconnect structure with bi-layer metal cap.
2. Description of Related Art
Integrated circuit chips typically include two or more levels of conductive lines which are vertically spaced apart and separated by intermediate insulating layers. Interconnections are formed between the levels of conductive lines in the chip for providing, for example, high wiring density and good thermal performance. The interconnections are formed by means of lines and vias which are etched through the insulating layers separating the levels. The lines and vias are then filled with metal to form interconnect features (i.e. via studs). A typical interconnect structure includes metal vias running perpendicular to the semiconductor substrate and metal lines running parallel to the semiconductor substrate. This process results in multiple levels of conductor wiring interconnection patterns, having individual levels connected by via studs, operating to distribute signals among the various circuits on the chip.
FIGS. 1A and 1B illustrate prior art interconnect or wiring structures including a dielectric layer 12 having a plurality of lines 14a, 14b and 14c formed therein. Lines 14a, 14b and 14c may be formed by first masking an insulating layer with photoresist and then selectively etching a portion of the insulating layer. Using well known photolithographic techniques, lines 14a, 14b and 14c are etched through a cavity formed in the photoresist to form an opening to dielectric layer 12 using isotropic or anisotropic etching processes. Following the etching of lines 14a, 14b and 14c and the removal of the photoresist, a barrier or liner layer 16 is deposited on the bottom and sidewall portions of the lines by means well known in the art. Liner layer 16 includes a material capable of lining the lines so as to prevent the diffusion of later deposited material.
With particular reference to FIG. 1A, lines 14a, 14b and 14c are then filled with a metal layer 18 using deposition techniques well known in the art. Metal layer 18 is then annealed and planarized. Metal layer 18 typically includes a conductive material, usually, Cu. Finally, a dielectric capping layer 20 is deposited over metal layer 18, diffusion barrier 16, and dielectric 12. The completed wiring structure is illustrated by FIG. 1A.
With reference to FIG. 1B, capping layer 20 may include a selectively deposited metal, such as CoWP resulting on a wiring structure having a Cu/metal interference with superior adhesion strength when compared to the typically used Cu/dielectric interface having enhanced electromigration resistance. Despite the improvement in electromigration resistance, however, the use of a metallic capping layer provides an interconnect structure with metallic residue present on a surface of the dielectric material between each conductive feature. This problematic metallic residue is illustrated in FIG. 1B. Specifically, FIG. 1B shows a prior art interconnect structure that includes a dielectric material 12 having conductive features embedded therein. The conductive features include a conductive material 18 which is located within an opening provided in the dielectric material 12. The conductive material 18 is separated from the dielectric material 12 by a diffusion barrier 16. A metallic capping layer 20 is present on the upper exposed surface of each conductive feature, i.e., atop the conductive material 18. As shown, metallic residue 22 forms on the exposed upper surface of the dielectric material 12 during the formation of the metallic capping layer 20. The presence of the metallic residue 22 between each of the conductive features hinders the reliability of the prior art interconnect structure and has delayed using metallic capping layers for the last three generations.
Accordingly, a need exist for a simplified method of forming interconnect structures having a metallic cap which overcomes the shortcomings of the prior art and which is compatible with existing integration schemes.